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cadapps

VLSI CAD Algorithm Visualizations implemented as Java Applications

conways-game-of-life

delete.me2

test, check if we can push etc

ece414-examples

RP2040 Sample Code for ECE 414 at Lafayette College

flowreg-dally

Register with ready-valid flow control based on Dally & Harting Example 22.1

hw_pq

A family of hardware priority queue implementations

l4_pci_32x32

L4 Maze Routing Accelerator

led_matrix_controller

FPGA Hardware to control the AdaFruit 16x32 LED Matrix.

life_core

Hardware Core for Conway's Game of Life

mazerouterapp

Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)

mips_l_multi

This is a modified version of the Single-Cycle MIPS processor design from Digital Design and Computer Architecture" (2nd ed.) by David M. Harris and Sarah L. Harris (Morgan-Kaufmann, 2013).

mips_l_pipeline

mips_l_single

Extended MIPS single-cycle pedagogical design from Harris & Harris "Digital Design and Computer Architecture"

newchannelrouter

otieno_research

Summer Design Projects with Maurice Otieno

placementapp

Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement

sr_pq

Shift Register Hardware Priority Queue

steinerapp

Visualization of rectilinear Steiner and Minimum Spanning Trees

sv_examples

SystemVerilog examples - common building blocks

sw_pq

Various software implmeentations of priority queues, including a Java implementation of the heap-based priority queue described in Ch. 5 of Cormen, Leiseson, Rivest & Stein

systolic_pq

A SystemVerilog implementation of Lieserson's Systolic Priority Queue

tsp_simulator

Tiled Spatial Processing Simulator

valid_ready

SystemVerilog implementation of Valid-Ready Interface