Simulation of VHDL files about knn-stuff HOT 4 CLOSED

Hi, M.H. Gholamrezaei,

It is indeed possible to simulate the Programmable Logic component of kNN-STUFF (accelerator) using a standard HDL simulator. However, note that the operation of the accelerator is deterministic, meaning that the execution time of a given workload is fixed and can be calculated using the models presented in this document.

If you still want to simulate the HDL, you will have to understand the communication flow between the processor and the accelerator first. For that, take a look at this file and how to compile datasets for knnsim (to understand what data is being passed and in what order to the accelerator). Also, you must know how AXI interfaces work, since the accelerator uses AXI-Stream interfaces to communicate.

However, once again, I advise you to use the existing models to predict the performance and throughput of the accelerator. I can hardly imagine that anything can be learned from simulating the HDL files (which will take a lot of time and effort).

Also, note that if you are interested in assessing the performance of the overall system (including the part executing in the ARM CPU), you can only do so using a Xilinx SoC, since there is no easy way of simulating the ARM CPU in this context.

I hope that you find this information helpful.

from knn-stuff.

Thank you for your quick reply.

Actually, my goal is to change the structure of the accelerator (e.g. using fixed-point arithmetic) and see the impact of this change on performance and hardware cost. I want to make sure that my design works with HDL simulation. Have you written any testbench for a single accelerator?

from knn-stuff.

Hi again,

I managed to find some simulation files. You can find them here.

I hope this helps!

from knn-stuff.

I appreciate your help. Good luck!

from knn-stuff.