jusan-zyh Goto Github PK

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

dataease

人人可用的开源数据可视化分析工具。

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

dma_ip_drivers

freerdp

FreeRDP is a free remote desktop protocol library and clients

freerdp-webconnect

A gateway for seamless access to your RDP-Sessions in any HTML5-compliant browser

git

Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documentation/SubmittingPatches procedure for any of your improvements.

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

hello-world

just another repository

iverilog

Icarus Verilog

jnidemo

a JNIDemo for zyh

jusan-zyh.github.io

hexo个人博客

learngit

litejesd204b

Small footprint and configurable JESD204B core

litescope

Small footprint and configurable embedded FPGA logic analyzer

litex

Build your hardware, easily!

marktext

📝A simple and elegant markdown editor, available for Linux, macOS and Windows.

milkdown

🍼 Plugin driven WYSIWYG markdown editor framework.

mygitremote

myhdl

The MyHDL development repository

openmmlabcourse

OpenMMLab course index and materials

pcie_analyzer

PCIe analyzer experiments

quasar

Remote Administration Tool for Windows

qwidgetexe2

Qt编写的一些项目的可执行文件，包括对应的说明文档、运行截图等，项目都是商业级别，如有需要完整源码或者定制功能请联系购买，QQ：517216493 微信：feiyangqingyun 推荐加微信。

remote-desktop-control

远程桌面控制(Spring+Netty+Swing)

rustdesk

Open source virtual / remote desktop infrastructure for everyone! The open source TeamViewer alternative. Display and control your PC and Android devices from anywhere at anytime.

sumatrapdf

SumatraPDF reader

tdc-core

A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

verilog_udp_tcp

Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.

wb2axi

Wishbone to ARM AMBA 4 AXI