kholoud-ebrahim Goto Github PK
Name: Kholoud Ebrahim
Type: User
Bio: Digital Verification Enthusiast
Blog: [email protected]
Kholoud Ebrahim's Projects
add_sub
Functional Verification of Add_Sub Design using UVM methodology with Various Versions such as a Basic UVM Tb, adding a Configuration Object to the Tb, Using the Virtual Sequence and Virtual Sequencer Concept, etc.
adder
implementation and test bench using System Verilog
alu
Verification of ALU using System Verilog, The 1st project for ITI 3 Months Digital Verification Track.
alu-8bit
Using an 8-bit full-adder/subtractor to create an 8-bit ALU.
alu_design_verification_uvm
implementation and test bench using UVM
apb_register_file
UVM based Verification of APB Register File. The UVM Env includes RAL Model. The simulation results contain functional and code coverage reports.
bitwise
UVM based Verification of Bitwise Operations Design. The UVM env includes Configuration Object for each agent and also the env, also it includes Virtual Sequences and Virtual Sequencer. The simulation results contain functional and code coverage reports.
explore-us-bikeshare-data
Using Python to understand U.S. bikeshare data. Calculating statistics and building an interactive environment where a user chooses the data and filter for a dataset to analyze.
hmc_controller_verification
HMC (Hybrid Memory Cube) Controller Verification Graduation project under the supervision of Si-Vision.
i2c_master
Implementation and Functional Verification of I2C Master using UVM methodology.
mac-unit
Perform a behavioral simulation of the top-module design, and run the simulation for 5 cycles.
sbqm
The manager of the Safebank bank branch, located in a nearby mall, is proposing to install an embedded system to monitor the client queue in front of the tellers. The proposed system, called SBqM™, is to display various information about the status of the queue.
spi_protocol
UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
synchronous_fifo
A simple synch FIFO designed in Verilog and verified in UVM methodology including scoreboards, coverage collector, also code coverage and functional coverage reports etc.
system-verilog-tasks
The third phase tasks in Chipions Program Training.
uart-tx
implementing Universal Asynchronous Receiver/Transmitter [TX]
uart_protocol
Functional Verification of UART Protocol using UVM methodology. A Serial Inter System Communication Peripheral Protocol.
up_down_counter_4bit
implementation and test bench using System Verilog
wrangle-and-analyze-data
Gathering data from a variety of sources and in a variety of formats, assessing its quality and tidiness, then cleaning it. Showing the wrangling efforts through analyses and visualizations.
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