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0402py

100-repoopen-lane

100daysofrtl

100 Days of RTL

2021_spring_nctu_iclab

NCTU 2021 Spring Integrated Circuit Design Laboratory

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

4k_60fps_me

Motion Vector Estimaion on 4K@60fps Video 运动向量估计硬件电路设计

advanced-physical-design-using-openlane-sky130

This repository documents my work from the Advanced Physical Design Using OpenLANE/Sky130 Workshop conducted by VLSI System Design. The objective of this workshop project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

advanced-physical-design-using-openlane-sky130-1

Advanced Physical Design using Openlane Sky130_ver2

advanced_openlane_workshop-documentation

Its a workshop conducted by VSD team

advancedsynthesisandstawithdc

aftx05_public

aham3soc

SoC Based on ARM Cortex-M3

aladdin

A pre-RTL, power-performance model for fixed-function accelerators

analysing-the-effect-nbti-phenomenon-on-snm-in-hspice

Analysing the effect NBTI Phenomenon on SNM in SRAM Cells

archfp

ArchFP is a floorplanning tool targeted towards prototyping of pre-RTL CMP design concepts.

arm_documents

Documents for ARM

asap7_reference_design

reference block design for the ASAP7nm library in Cadence Innovus

asap7_snps

Supplemental technology files for ASAP7 PDK with Synopsys design flow

asic-design-example-risc-cpu

Base on Synopsys platform using VCS,DC,ICC,PT.

asic-vlsi

Verilog and Synthesis Files from ASIC VLSI projects

asic_labs_sp22

asicmethadology

aspdac-2022-tutorial

awesome-hardware-tools

List of awesome open source hardware tools

awesome-opensource-hardware

List of awesome open source hardware projects

aws-eda-workshops

Samples and documentation for deploying EDA computing environments in AWS

axis_tek_python_scripts

bag_xbase_demo

basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

beginner-soc-physical-design-workshop

This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.