Comments (1)
laforest
commented on May 11, 2024
Can Verible and Surelog lint for only the synthesizable subset of Verilog-2001, rather than SystemVerilog?
I use a subset of that subset when writing code to maximize portability and to reduce the number of bugs from Verilog corner-cases and varying support from CAD tools.
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Related Issues (9)
- Missing Width_Extender module HOT 1
- Possible syntax error at Pipeline_FIFO_Buffer.v HOT 2
- CAM implementation HOT 2
- Consider deploying to github pages HOT 2
- Problems with zero or negative widths HOT 10
- Verilator complain about Carryin_binary.v HOT 1
- Constant.v:24: warning: @* found no sensitivities so it will never trigger. HOT 2
- Function body with multiple statements requires SystemVerilog HOT 3
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