leochand101 Goto Github PK
Name: Cramamur
Type: User
Bio: Senior Scientist with Alphacore, Circuits, EDA, auto-place and route, CAD, Testing, modelling are some of my interests. PhD in EE with ASU
Cramamur's Projects
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
doc_history
History of random searches and examples
freerouting
Printed Circuit Board Routing Software from FreeRouting.net
gdsfactory
Python package to generate GDS layouts.
handson-ml2
A series of Jupyter notebooks that walk you through the fundamentals of Machine Learning and Deep Learning in Python using Scikit-Learn, Keras and TensorFlow 2.
kicad_freerouting-plugin
KiCad FreeRouting.jar round trip invoker
open-gpgpu-flexgrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
openfasoc
Fully Open Source FASOC generators built on top of OpenROAD
openfpga
An Open-source FPGA IP Generator
opentimer
A High-performance Timing Analysis Tool for VLSI Systems
pybert
Serial communication link bit error rate tester simulator, written in Python.
pyoa
Donald Amundson's Python interface to OpenAccess IC design data API
pyspectre
Python interface for Cadence Spectre
pyspice
Simulate electronic circuit using Python and the Ngspice / Xyce simulators
skidl
SKiDL is a module that extends Python with the ability to design electronic circuits.
sky130_klayout_pdk
Skywater 130nm Klayout Device Generators PDK
sofa
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
tf_import
Reads a Cadence techfile into KLayout and produces layer properties from it
verigpu
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
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