Add support for lowering vectors of wires from FIRRTL to RTL about circt HOT 9 CLOSED

Generally for memory inference to work you want something like:
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];

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@lattner I think option 2 is most intuitive.

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It could be good to bring this up on the forum to see if others have an opinion, it would also be worth looking at what LLHD is doing here.

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Interesting, is the 'packed vs unpacked' distinction just simulator performance, or is there something else going on here?

It seems like there are a couple of ways we could model this:

1. we could model this with a list of dimensions, then a "number of packed dimensions" integer in the type.
2. we could model this as a single "packed vector" and "unpacked vector" type that compose onto each other.

I think the major distinction should be how these compose with non-bit types like the SystemVerilog bundle types.

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FYI https://www.veripool.org/issues/1656-Verilator--RFC-Relaxing-UNOPTFLAT-by-dividing-unpacked-array#note-1

Something to keep in mind when generating arrays b/c Verilator is the most used open source simulator.

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4D array

//      2     1        3     4
logic [1:5] [7:0] v4 [1:7] [1:8];

1,2 = packed dimensions - guaranteed to be represented as a contiguous set of bits.
3,4 = unpacked dimentions - can be resized (grow, shrink)

1 varies most rapidly, followed by 2,3,4

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All N packed dimensions have to compose first before to compose with M unpacked dimensions.
Could we make sure that packed type can compose into primitive or packed type only, while unpacked can compose into primitive, packed or unpacked.

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I'm not sure if we ended up discussing this in one of the meetings, but I'm planning on adding a tensor type to the RTL dialect. I welcome additional input!

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We now have ArrayType (packed) and UnpackedArrayType, I think this is done.

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