Comments (4)
Each of the output values in your picture matches the intended output for that situation.
The Switch connects the output to the input when it is on (i.e. 1) and disconnects it when it is off (i.e. 0). A disconnected output is not driven to any state and is thus floating (U), indicated by the blue color. All the switches in your picture are off (0).
If you provide inputs that have no known 0 or 1 value to a logic gate you will get an unknown result. It is not floating but an unknown logic value. That is designated in the simulator by an error (E) value displayed as red. It is a mistake to design hardware that uses such a value for further computations.
Likewise, using a U (blue) control value for a controlled buffer or inverter leaves the simulator with no way to display a meaningful output since it doesn't even know if it should drive the output or not. Thus that output is displayed as red (E) and should not be used.
So you should make sure your logic gates have well defined 0 or 1 inputs.
Read the Help for those components for more information.
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To add to @davidhutchens very good answer: If you want to continue using the Switch for controlling your inputs, you need to add Pull Resistors with Pull Direction set to Zero to ensure that the inputs of the gates have a well-defined value if the Switch disconnects the input from the Power.
from logisim-evolution.
Wow, this simulator is more advanced and much better than I thought.
I didn't specify very clearly the issue, unfortunately, looking back on my first message.
The issue is that my output is a 0 even when power is on the line.
I believe that @maehne's answer will do the trick, I will verify.
Excellent explanation folks, thank you.
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Yep, that fixed everything. Thanks team!
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Related Issues (20)
- Simulation Halted by Internal Error VHDL HOT 5
- Add a writable EEPROM with persistent data capability HOT 6
- Feature Request: ROM data width > 64 Bits HOT 1
- AppImage HOT 1
- wont save circuit after cancel HOT 4
- Shortcuts not working on Linux OpenSUSE and French keyboard HOT 1
- Maximum RAM address bit width unclear HOT 1
- Add a way to hide navigation bar
- Double warning message
- Combinational analysis malfunction in version 3.8 HOT 3
- Custom wire colors / multi-wire selecting HOT 1
- Wrong behavior of asynchronous RAM reads in generated VHDL HOT 4
- Nightly build failed for Mac HOT 6
- User interface is too bright HOT 1
- No X11 DISPLAY variable was set - Wayland HOT 2
- Simulation halted by internal error when generating timing diagram HOT 4
- Debian build and Linux release value HOT 4
- Splitter as Input / Output sub circuit port
- Remember camera position for each circuit
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