Comments (2)
@nbdd0121 Disallowing argumentless functions would work. I don't see many people using them. It seems the best use-case is just for style consistency for a group of related functions.
For example: https://github.com/pulp-platform/riscv-dbg/blob/138d74bcaa90c70180c12215db3776813d2a95f2/src/dm_pkg.sv#L420-L437
function automatic logic [31:0] csrr (csr_reg_t csr, logic [4:0] dest); // rs1, CSRRS, rd, OpCode System return {csr, 5'h0, 3'h2, dest, 7'h73}; endfunction function automatic logic [31:0] branch(logic [4:0] src2, logic [4:0] src1, logic [2:0] funct3, logic [11:0] offset); // OpCode Branch return {offset[11], offset[9:4], src2, src1, funct3, offset[3:0], offset[10], 7'b11_000_11}; endfunction function automatic logic [31:0] ebreak (); return 32'h00100073; endfunction
from style-guides.
By @a-will in #66 (comment)
// Equivalent variable declarations with initial values. logic foo = bar; var logic foo = bar; // Equivalent net declarations with continuous assignment. wire foo = bar; wire logic foo = bar;
Wow, I didn't know you could do this. I think this example should be added to the "Use logic
for synthesis" section. It may help stress the importance of the rule a bit more
from style-guides.
Related Issues (20)
- Use of functions and automatic HOT 6
- [UVM:styleguide] best end of test practices HOT 13
- Recommendations around xprop in simulations HOT 11
- [SystemVerilog] parameter vs. localparam in packages HOT 5
- [SV] Placement of closing parentheses in initializer lists HOT 3
- Scope of this style guide and questions HOT 3
- Prefer SystemVerilog-2017 instead of 2012 HOT 6
- How to align named ports in module instantiations? HOT 17
- Use of SystemVerilog Interfaces HOT 12
- [sv] How to format module instantiations that fit in a single line? HOT 5
- Guidance on whether to add space between SV keyword 'wait' and parenthesis HOT 3
- Linting file for spyglass HOT 5
- Parameter naming convention inconsistencies
- Stance on wand / wor? HOT 1
- Plagarism of the Google Verilog Style Guide HOT 2
- Inconsistent use of "simulation-synthesis mismatch" HOT 1
- FSM must be implement with two process blocks HOT 1
- typo in the **Suffixes** HOT 1
- Why is SV interface usage discouraged ? HOT 1
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from style-guides.