Comments (4)
Sayma uses the ARTIQ 4 bootloader currently (and there's no particular reason I know for it to go back). The Ultrascale SDRAM code in MiSoC could be useful for other people who use MiSoC on Ultrascale, not that any necessarily exist.
from misoc.
I don't fully understand the implications of these different paths. Are you proposing switching LM32 to mor1kx? Where would Ultrascale SDRAM support be housed if not in MiSoC? What caused it to stop working?
from misoc.
ARTIQ 4 no longer uses the MiSoC bootloader, and Ultrascale development continued in the ARTIQ bootloader but the changes were not ported to the MiSoC bootloader.
from misoc.
Since Sayma support is part of ARTIQ 4 it seems like Sayma ought to also use the ARTIQ 4 bootloader. What are the prospects for this port?
from misoc.
Related Issues (20)
- fix liteeth error counter atomicity problem HOT 2
- liteeth: remove dw parameterization HOT 2
- liteeth: rename dv to rx_dv
- liteeth: remove MII clock output
- clean up memory regions, names, offsets
- kasli/spi_flash: investigate and implement quad i/o read
- DDR3-related error in Vivado timing report for Ultrascale HOT 1
- spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider
- Record.connect return value not used HOT 3
- Binutils compilation
- Standard 1 bit SPI mode for spi_flash not available? HOT 2
- software not rebuilt after gateware change
- Wanted to Build a small SoC HOT 1
- CSRStorage with write_from_dev=True seems broken in simulation HOT 3
- register_rom weirdness HOT 2
- Wrong version in `setup.py`
- different clocking of differentiator and integrator HOT 3
- misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2 HOT 1
- pip install of tag 0.12 fails HOT 5
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