Undefined variable _XOR_EPI breaks builds with AVX512 on non Intel CPUs about elpa HOT 7 CLOSED

I tested compiling with different march settings with the GCC 13.1 compiler (the one I had easily available on that AMD system):
I can indeed reproduce the problem with -march=knl and -march=knm. However, I do not see it with -march=skylake-avx512 or (of course) -march=znver4.
@maxim-masterov could you please tell us what you set for -march in your case? Could you try with -march=skylake-avx512 with your GCC 11.3?

from elpa.

Hi @maxim-masterov ,

on which AMD CPU are you trying to compile ELPA and which compiler do you use?
We do not see this issue on AMD EPYC 9654 with the Intel compiler.

from elpa.

Hi @terminationshock ,
The CPU is AMD EPYC 9654 96-Core Processor and the compiler I use is GCC-11.3.0.

The error occurs because GCC11 doesn't support zen4 architecture. As a result, the evaluation of existence of AVX512 instructions by the configure.ac script results in the following output:

checking whether we compile for Xeon... no
checking whether we compile for Xeon PHI... yes

This leads to execution of this branch in the configure.ac script:

The _XOR_EPI macro is undefined (or I haven't found a place with its definition). So, the above snippet of code is getting converted to a casting of an integer into a packed double instead of invocation of the XOR operation.

from elpa.

I think something happened between the two releases 2020.05.001 and 2020.11.001

In 2020.05.001 the XOR operation looks correct:

from elpa.

I used -march=znver2. I can try -march=skylake-avx512, but I don't have access to Genoa CPUs at the moment. Should get it back next week. I will report as soon as I get some results.

Although, -march=skylake-avx512 (I'm sure) will help building the code, it won't resolve the problem with an undefined macro, right?

from elpa.

Yes, we will look at the macro anyway.

However, I am a bit puzzled that the configure detects AVX-512 instructions anyhow with -march=znver2. In the gcc 11 manpage, it does not list AVX-512 for this flag:

znver2
               AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16,
               MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, WBNOINVD, and 64-bit instruction set extensions.)

from elpa.

@terminationshock Just to confirm, the -march=skylake-avx512 indeed allowed the build to finish

from elpa.