masterplayer Goto Github PK
Type: User
Bio: FPGA developer. This repositories consists of many components of MasterPlayer foundation
Type: User
Bio: FPGA developer. This repositories consists of many components of MasterPlayer foundation
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
FPGA Based reconfiguration interface from AXI to SPI Analog Device, holds readed data and sends data from AXI to AD over SPI/SDIO interface
ARP Table based upon true dual port ram with support setting number of elements
AXI Lite register file for registers with configurable count of registers
Full-Duplex support memory manager for transmit data from S_AXIS and sending data to M_AXI_FULL, or receive data over M_AXI_FULL and sending data to M_AXIS
AXI controlled timer for measurement average time of performance
AXI-Stream data generator with support AXI-Lite configuration
Компонент для выполнения команд чтения из памяти и отправки значений на шину AXI-Stream. Система прерываний не поддерживается
Component for writing to DDR memory over AXI interface from AXI-Stream to AXI full with support interrupts
Component for writing data from axi-stream to axi-full with support interrupt signal for each packet. packet size cannot greater MAX_BURST words count. Simple component
axi-stream data checker for indication about errors and statistics counters
AXI-Stream data collector grouped by ID, USER. Component Accumulates input data streams, and establish this data, when quantity of them exceeds limit
threshold controller for limit data speed on AXI-Stream bus with sync/async support
simple udp packager for incapsulate input stream to udp datagrams
parametrized UDP packet former with support various widths and header size
Component for incapsulate input data to UDP datagrams with Eth/IP/udp headers with various size support
Library for processing and configuration adxl345 from FPGA with control from processor
FPGA implementation I2C bridge with support AXI-Stream protocol
axi-stream output register for alternative output fifo
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
FPGA bitstream loader for xilinx using SelectMAP
Bitstream loader for Xilinx FPGA over AXI-Stream bus
i2s receiver data from digital microphone writed on SystemVerilog
simple demo hardware code for implement access to ST7789 LCD display from FPGA
Micron Flash interface with support x4 data width and supports AXI-Stream interface
IRQ generator with configurable duration
interrupt retry engine for regenerate interrupts signal
RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support
System Monitor/Manager DRP controller for reading data from IP core over DRP protocol
projects, sources, files for working in xilinx sdk.
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