mdzakirhussain Goto Github PK

adder_test1

advanced-physical-design-using-openlane-sky130

analog-design-modelling

Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)

approx-fpgas

Approximate arithmetic circuits for FPGAs

atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

basic-verilog

caravel_adder_project

https://caravel-user-project.readthedocs.io

caravel_adder_project1

dff

drum

The Verilog source code for DRUM approximate multiplier.

embedded-systems-with-8051

All the resources for Embedded Systems with 8051 Online Training Course on Kitflix.com

fault

Automatic test pattern generator (early alpha).

iverilog

Icarus Verilog

myhdl123

open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

openlane

openlaneinstallation

opensourceeda

This repository will help you to install opensourceEDA Tools

opensourceeda-1

opensourceedav1

This repository will help you to Install and to test the Installation correctness of the opensourceEDA Tools.

opensourceedav2

opensourceedav3

opensourceedav4

pythnon_learning

qca-basics

QCA Examples

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs

replace

RePlAce global placement tool

rtldesignusingverilogwithsky130technology

RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.

simple_spi

sv