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apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

atmega-xmega-soft-core

Mega/Xmega soft core RTL design.

blog_yosyshq

edalize

An abstraction library for interfacing EDA tools

embench-iot

The main Embench repository

embench-tester

esr31web

fazyrv

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

fazyrv-exotiny

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

json.sv

SystemVerilog package for reading, manipulating, and writing JSON-formatted data

kostalpikopy

A package for working with a Piko Inverter from Kostal

litex

Build your hardware, easily!

logip

Logic Analyzer IP Core

max7219_dotmatrixdisplay

an c++ Arduino library to drive a string of MAX7219 dot matrix displays

nextpnr

nextpnr portable FPGA place and route tool

nextpnr-tests

nokia_5110_design_clock

[WIP] A little project using a Nokia 5110 display and an Arduino Nano + DS3231 RTC to build a neat clock.

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

qerv

rv32i_sc_logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

smsbox

This fun project receives text messages (sms) and prints them via the thermal printer

sock.sv

A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.

tinybricks

Bootsector bricks game

tt03-another-piece-of-pi

Tiny Tapeout 03: Another Piece of Pi

tt05-submission-template

Submission template for Tiny Tapeout 05

tt06-fazyrv-exotiny

vcd

VCD file (Value Change Dump) command line viewer