Related Issues (20)
- CSRs that can be accessed without `PERMIT_ACCESS_SYSTEM_REGISTERS` should be specific to compartments HOT 13
- Allowing delayed check for jump/branch instructions HOT 15
- Extending support for DII execution mode HOT 5
- Sealing and Unsealing Authorities for addresses rather than otypes HOT 4
- Simplify MEPCC / MTCC legalisation HOT 2
- Specify background zeroizer
- Specify background revoker
- MCAUSE/MTVAL for illegal SCR addresses HOT 2
- Intended use for reserved bit in capabilities HOT 2
- Libraries accessing Read/Write data through caps stored within PCC HOT 4
- CSub redundant? HOT 1
- v2? isentry support
- v2: Split sentries by direction HOT 1
- v2? cgp as SCR
- Optimise bounds encoding HOT 1
- misa reports incorrect value in Sail HOT 1
- Type error while building with upstream Sail HOT 4
- Have CJALR create !G sentries? HOT 6
- Incorrect behaviour when registers greater than 15 used as destination in certain instructions HOT 1
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