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capture_data_gui

chisel

A fast TCP/UDP tunnel over HTTP

chisel3

Chisel 3: A Modern Hardware Design Language

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

crossbar

digital-ide

在vscode上的数字设计开发插件

dma_ip_drivers

Xilinx QDMA IP Drivers

e200_opensource

The Ultra-Low Power RISC Core

fft-dit-fpga

Verilog module for calculation of FFT.

first-pr

《GitHub实践入门》实验用仓库

hbird-e-sdk

Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/

hugotalks

icestudio

:snowflake: Visual editor for open FPGA boards

ieee1588-ptp

An IEEE1588 Precision Time Protocol Implementation written in Python and C using a kernel bypass.

jesd204b

JESD204B core for Migen/MiSoC

latex_module

latexdoc

用于LaTeX命令速查

logic_analysis

本工程用FPGA和python实现一个简单的8路输入逻辑分析仪

minefujiko.github.io

mips-cpu

MIPS CPU implemented in Verilog

mt32_rand_gen

Mersenne Twister Pseudo Random Number Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).

my-vscode-verilog-ext

my_config_files

my_hdl

myhdl

The MyHDL development repository

notepad_plugins_for_verilog

Notepad++ plugins for verilog based on Python Script

notepad_python_script

ofdm

A MATLAB program to help understand OFDM.

open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design