mohamedsherifnoureldin Goto Github PK

bitebuddy

An AI powered personalized meal-planning tool and chatbot. Web Application built using React and OpenAI's APIs

codelygptapi

fcarve

Python-based Digital Forensic tool to carve hidden files based on magic bytes and merge multiple files together

huffman-coding-text-compression

A C++ program that compresses text files using the Huffman Coding algorithm. This program was written as a final project for my Data Structures and Algorithms class (CSCE2202).

mohamedsherifnoureldin

Config files for my GitHub profile.

pctrl

Rust based Linux Process Manager with both a GUI and a TUI

qt-tom-jerry-maze-game

A C++ Qt game based on the classic Tom & Jerry cartoon but with a theme of playing in space. This game was created as a project for the Fundamentals of Computing II course (CSCE1101).

risc-v-simulator

RISC-V RV32I Assembly Simulator is a C++ program that allows one to test and simulate assembly programs by showing the contents of registers along with the memory after each instruction execution. This program was written as a project for the Computer Organization and Assembly Language Programming course (CSCE2303).

simulatedannealing

C++ Implementation for the Simulated Annealing algorithm used for cell placement for the Digital Design II course with possibility of generating graphs and GIFs

teachersearch

tomasuloscheduler

A C++ simulation of the dynamic Tomasulo instruction scheduling algorithm (without speculation) on the RiSC-16 architecture. Implemented as the CSCE 3301 (Computer Architecture) course's second project, in Spring 2023.

verilogalarmclock

A Digital Clock/Alarm System implemented using Verilog. The project was created using Vivado software and implemented on the Basys 3 FPGA board. This project was created for the Digital Desgin I (CSCE 2301) course.

verilogpipelinedriscvprocessor

A verilog implementation of a pipelined processor for the RISC-V architecture, with support for all 40 instructions of the RV32I instruction set; as well as an additional 8 for the RV32M instruction set. Supports implementation on a Nexys A7 board. Implemented as the CSCE 3301 (Computer Architecture) course's first project, in Spring 2023.