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aes

Advanced Encryption Standard (AES) modelling, using Verilog HDL.

basicblocks

This Repo contains RTL codes for basic logic blocks (eg. Counter, mux … etc.), using Verilog HDL.

communicationsystem

computationalmath

dsp

Term 7 DSP Labs

image-processing

Implementing image processing algorithms using Verilog HDL.

ir-txrx

IR-RC5 Protocol Tx-Rx modeling in SystemVerilog HDL and Vivado 2018 IDE

lfsr

Decryption Using LFSR, Modelled using System Verilog HDL

maged_hotelreservationsystem

mips-processor

Implementation of 32-bit MIPS-processor using SystemVerilog HDL

pig

Smart Pipeline Inspection Pig Control Logic, modelled in Verilog

rudimentary-games-console

Development of a Rudimentary Games Console, using Verilog HDL.

signal_generator

spi

SPI Protocol Implementation using SystemVerilog HDL

tlcalculations

uart

UART implementation using verilog

uart-contributor

Contributor of implementing UART transmitter using Verilog

washing-machine