Name: Muhammad Talha
Type: User
Company: MicroElectronic Research Lab
Bio: B.E Computer Engineering Student | UIT University | Research Trainee at Merl | system verilog | verilog | verilator |python | C++
Twitter: MTALHA91345
Location: Karachi, Pakistan
Muhammad Talha 's Projects
Ariane is a 6-stage RISC-V CPU
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
This is c++ repository which is based on implementation of oops topics like single , multiple and multilevel inheritance
Football management system DBMS python GUI project repository . This project is design on mysql database with python tiknter library for making a gui for the user
My GitHub Profile README. Don't just fork, star it ⭐, so others can find it too! 🤝. Contributors are welcome.Feel free to contribute on my readme to make it more awesome 🔥🔥
Oops object oriented programming language.This repo is basically a learning journey that how you implements the oops concepts in c++
This is my openlane repository in which we perform synthesis of our design/module.
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
In this repo you will get the step by step implementation of Rv32i processor from the Basic instructions to the 5-stage pipeline.Tool used for this are verilator and Vivado
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
An implementation of rv32i single cycle processor on logisim
🟩⬜ Generates a snake game from a github user contributions graph and output a screen capture as animated svg or gif
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
Verilog is a hardware description language. This repo is basically a learning journey of verilog