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theta.yang's Projects

axi icon axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

corundum icon corundum

Open source, high performance, FPGA-based NIC

dromajo icon dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

dynaconf icon dynaconf

Configuration Management for Python ⚙

firesim icon firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

ibex icon ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

logic icon logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

mini-arm-os icon mini-arm-os

Build a minimal multi-tasking OS kernel for ARM from scratch

opentimer icon opentimer

A High-performance Timing Analysis Tool for VLSI Systems

opentitan icon opentitan

OpenTitan: Open source silicon root of trust

riscv-dv icon riscv-dv

Random instruction generator for RISC-V processor verification

uvmc icon uvmc

Connecting SystemC with SystemVerilog

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