Comments (4)
lib. prepared, now verifying license
from hwt.
Still not consulted with all the participants due tasks with higher priority.
New deadline is 2018-09-xx
from hwt.
Last meeting will be 2018-09-05.
Now it seems HWIO library can go opensource and everyone is happy about it.
Features:
- Linux like bus-device architecture, but in C++
- user space lookup and mmap of device by compatibility string or name from dts
- dynamic spooting of devices, device loading from XML/json
- client-server for access of remote devices, mmap for local devices, dynamically added server corutines
- virtual devices dynamically generated by simulation
- device origin does not matter, one server instance can contain real and virtualized devices and also can connect to another server
from hwt.
Confirmed, lib will appear in repositories and on github probably this weekend.
from hwt.
Related Issues (20)
- Proper tutorial - components, interfaces HOT 2
- Proper tutorial - compilation phases and serialization customizations, vendor tools integration HOT 2
- Proper tutorial - simulations/verifications HOT 2
- Prevent from dupliacation of generic/params if it shares same value HOT 1
- Proper tutorial - python project packaging and distribution, doc, visualization HOT 1
- rm relicts of interface direction discoverry logic HOT 1
- Multiple component variants for specified parameter combinations under wrapper HOT 2
- Convert interfaces to HDL as well (VHDL records, SV interface)
- Support for formal verification statements HOT 2
- IP core importing HOT 3
- Complete tests for RtlSignals generated from composed types like HStruct, HArray HOT 1
- Tests for replace_input_in_expr HOT 1
- Tests for StructIntf._eq/__ne__ operators HOT 1
- Complete tests for assignments to a cast or slice of registers HOT 1
- Issues with basic example HOT 3
- add_param_asserts breaks examples HOT 5
- assigment semantics unclear HOT 2
- Instantiate VHDL or Verilog IPs as black-boxes HOT 2
- Native Async reset support in RtlNetlist? HOT 4
- Incorrect initialization with Verilog serializer HOT 3
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