TOD clock should be 24bit about cia-verilog HOT 2 CLOSED

Yes I believe you are right. I found this thread, http://eab.abime.net/showthread.php?t=99688, after I had published the design, but I haven't gotten around to update the code. I also currently don't have hardware to test the design with, so I haven't had enough incentive to do the change I suppose. But thanks for reminding me; I will keep the issue open until it is eventually fixed.

from cia-verilog.

No problem, I quickly hacked up something akin to what I think it should look like and it seems to just about fit in an XC95288XL according to the Xilinx compiler (there was an issue where async and sync assignment is mixed in a block which I needed to fix first but I forget where now). So I guess it is a toss-up between that and MAX II/V with level shifting to play with it.

from cia-verilog.