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Nick Iliev's Projects

alu_4_bit_4_ops_mitll_fdsoi_process icon alu_4_bit_4_ops_mitll_fdsoi_process

ALU with 4 operations 1) 4 bit carry look ahead adder 2) 4 bit 1’s complimentary 3) 4 bit 2’s complimentary 4) 4bitAddtraction in 4 bits, done in process mitll_fdsoi, schametics to layout

analog-cmos-systems-and-circuits-for-2d-3d-localization icon analog-cmos-systems-and-circuits-for-2d-3d-localization

This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coordinates. Optical or Infrared Angle-of-Arrival , AOA, (noisy) measurements from each anchor to the uknown target are assumed available.

innovus_nanoroute_rt01_routed_testcases_blocking-clk_path icon innovus_nanoroute_rt01_routed_testcases_blocking-clk_path

Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level

rng_self_calib icon rng_self_calib

Digital CPU peripheral module for calibration of a pseudo-random-number generator. In CMOS gsclk45 nm, verilog RTL-Compiler (RC) synthesis and Innovus placement and layout.

spiking_neural_synapse_cmos180 icon spiking_neural_synapse_cmos180

Analog circuits for a Spiking Neuron (and Synapse) in CMOS 180 nm, Cadence ADE XL (Monte Carlo) and ADE_L (Nominal) simulations.

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