Comments (1)
Thanks for reporting. The VCS backend should definitely support VHDL too. As I don't have access to VCS myself I would very much appreciate if some VHDL user with access to VCS could help out. Happy to review patches
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Related Issues (20)
- Use ninja files by default in the Flow API HOT 1
- ModelSim makefile is problematic on Windows
- Improve SymbiFlow backend HOT 7
- Radiant file types need to include systemVerilogSource
- Support external tools and flows HOT 2
- flow options need to be applied before tool options HOT 1
- vopt_options missing in modelsim.py HOT 4
- Vivado method missing for programming FPGA (with fusesoc) HOT 6
- Yosys, arch=xilinx fails because of syntax error in write_blif command HOT 1
- F4PGA/Symbiflow Backend HOT 12
- PNR key-value pair gets lost when running vivado HOT 1
- Ip cores provide to bd file in Vivado did not add to project and updated.
- usage of packages and tool classes HOT 1
- EDAM file: toplevel list of string HOT 1
- vivado xsim support for xci or xilinx ip HOT 5
- Vivado block design support is broken
- explicit dependencies for vunit
- quartus qsys path seperator on windows 10
- gnu make on windows 10 HOT 1
- Support for Questasim HOT 1
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