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olofk avatar olofk commented on July 23, 2024

I wonder if this might work

--- a/edalize/templates/vivado/vivado-program.tcl.j2
+++ b/edalize/templates/vivado/vivado-program.tcl.j2
@@ -14,7 +14,11 @@ connect_hw_server
 
 # Find the first target and device that contains a FPGA $part.
 set hw_device_found 0
-foreach { hw_target } [get_hw_targets] {
+if {[catch get_hw_targets hw_targets]} {
+    exit 1
+}
+
+foreach hw_target $hw_targets {
     puts "INFO: Trying to use hardware target $hw_target"
 
     current_hw_target $hw_target

Don't have access to a board right now to test the working case but it seems to fail nicer at least :)

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imphil avatar imphil commented on July 23, 2024

I can give it a try in the new year.

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olofk avatar olofk commented on July 23, 2024

Are we happy with it now?

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andmeyee avatar andmeyee commented on July 23, 2024

Is there any progress on this issue? The generation of a bitstream file without the need to program a connected device would be nice.

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olofk avatar olofk commented on July 23, 2024

I agree. In hindsight it was a questionable choice to try and program boards by default and most of the new FPGA backends don't have this functionality. In the long run I think there should be some extra config in the target sections to define how and if the board should be programmed. There's also some more thoughts about this here.

Oh, wait a minute. The easiest thing you can do right now is to add --build to the command parameters. That way FuseSoC will stop after creating the bitstream

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andmeyee avatar andmeyee commented on July 23, 2024

Ok, that helps for the moment. Thanks a lot for the hint.

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