Comments (3)
Can you try the vcom branch and see if it does the trick?
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That works perfectly, thank you!
from edalize.
Great. Thanks for reporting and checking
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Related Issues (20)
- Vivado block design support is broken
- explicit dependencies for vunit
- quartus qsys path seperator on windows 10
- gnu make on windows 10 HOT 1
- Support for Questasim HOT 1
- support for include file in yosys HOT 2
- yosys: wrong target name in Makefile, if output_name tool option is used
- Disabling yosys's synthesis HOT 1
- Testsuite fails intermittently HOT 6
- Skipping bitstream generation in vivado HOT 8
- How best to fix filelist backend HOT 3
- filelist.py uses python 3.8 syntax HOT 5
- Why is the user guide html that I generated empty. HOT 3
- Efinix FPGA support HOT 8
- ImportError: cannot import name 'get_edatool' from 'edalize' (unknown location) HOT 4
- Xcelium: file list HOT 1
- Modelsim missing in tools
- Support a Vivado IP-packaging flow HOT 2
- Simulating Vivado IPs (xci, bd) HOT 4
- `make_libraries_directories` on Windows fails due to `mkdir -p` HOT 3
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