Support Synopsys Design Compiler (DC) for Synthesis about edalize HOT 4 OPEN

#####################
##  PREPARE FLOW   ##
#####################

# this is a setup script that the user needs to provide (see template below). 
source setup.tcl

# paths
set WORKLIB  "WORK"
set REPDIR   "REPORTS"
set DDCDIR   "DDC"
set VLOGDIR  "NETLISTS"

exec mkdir -p ${REPDIR} ${DDCDIR} ${VLOGDIR} ${WORKLIB}

# define work lib path
define_design_lib WORK -path $WORKLIB

#######################
##  DESIGN SOURCES  ###
#######################

# define the top level 
set TOP_ENTITY <TOP_ENTITY_NAME>

# read source list generated by fusesoc
set fp [open [ls "*.scr"] r]
set file_data [read $fp]
close $fp
set data [split $file_data "\n"]

# if needed, this define can be used to selects the appropriate technology 
# by defining PRIM_DEFAULT_IMPL=prim_pkg::Impl<tech identifier>
# TECH_LIB_SEL is set inside the library setup script
set DEFINE "PRIM_DEFAULT_IMPL=<PRIM_DEFAULT_IMPL> "

# parse out the SV +defines that Fusesoc puts into the source list
set SRC {}
foreach item $data {
	if {[string range $item 0 7] == "+define+"}  {
		set DEFINE "${DEFINE}[string range $item 8 end] "
	} else {
		lappend SRC $item
	}
}

# additional parameter override (empty at the moment, 
# could be passed through by fusesoc as well in a similar way as +define)
set PARAMS ""

###########################
##   ELABORATE DESIGN    ##
###########################

# delete previous designs.
remove_design -designs
sh rm -rf $WORKLIB/*

analyze -define ${DEFINE} -format sv ${SRC}    > "${REPDIR}/${TOP_ENTITY}_analyze.rpt"
elaborate  ${TOP_ENTITY} -parameters ${PARAMS} > "${REPDIR}/${TOP_ENTITY}_elab.rpt"
link                                           > "${REPDIR}/${TOP_ENTITY}_link.rpt"

write_file -format ddc -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_elab.ddc"
write_file -format verilog -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_elab.v"

###########################
##   APPLY CONSTRAINTS   ##
###########################

# user needs to supply a constraints file, see below for a template
source constraints.tcl

######################
##    MAP DESIGN    ##
######################

# gate_clock, scan and no_autoungroup are all options that are typically used
# maybe we can add a tool parameter like "compile_ultra_switches", which contains a list of these
compile_ultra -gate_clock -scan -no_autoungroup > "${REPDIR}/${TOP_ENTITY}_compile.rpt"

#################
##   REPORTS   ##
#################

# write NAND2 equivalent to file for the reporting scripts
sh echo ${NAND2_GATE_EQUIVALENT} > "${REPDIR}/${TOP_ENTITY}_gate_equiv.rpt"

report_clocks                                 > "${REPDIR}/${TOP_ENTITY}_clocks.rpt"
report_timing -nosplit -slack_lesser_than 0.0 > "${REPDIR}/${TOP_ENTITY}_timing.rpt"
report_area   -hier -nosplit                  > "${REPDIR}/${TOP_ENTITY}_area.rpt"
report_power  -hier -nosplit                  > "${REPDIR}/${TOP_ENTITY}_power.rpt"
report_constraints -all_violators             > "${REPDIR}/${TOP_ENTITY}_constraints.rpt"

report_timing      -nosplit -nworst 1000 -input -net -trans -cap > "${REPDIR}/${TOP_ENTITY}_timing_long.rpt"

#################
##   NETLIST   ##
#################

change_names -rules verilog -hierarchy
write_file -format ddc     -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_mapped.ddc"
write_file -format verilog -hierarchy -output "${VLOGDIR}/${TOP_ENTITY}_mapped.v"

# do not include in interactive modes
exit

########################
##    TOOL SETUP      ##
########################

# this depends #available licenses and compute environment
set_host_options -max_cores 1

########################
##   LIBRARY SETUP    ##
########################

# path to synopsys installation
set SYNOPSYS_PATH   "<SYNOPSYS_PATH>"  
# paths to standard cell and sram db files
# this is just an example
set STDCELL_DB_PATH "<STDCELL_DB_PATH>" 
set SRAM_DB_PATH    "<SRAM_DB_PATH>" 

# library name prefix
set VARIANT  "<MY_LIBRARY>"

# corners to use
# it is advisible to use worst case 
# (i.e. wc or ss corners at high temp like 125c)
set STDCELL_CORNER "<TECH_CORNER>"
# select memory corners
set SRAM_CORNER    "<TECH_CORNER>"

# this could eventually be moved into .synopsys_dc.setup
set search_path [list .                                  \
                      "${SYNOPSYS_PATH}/libraries/syn"   \
                      "${SYNOPSYS_PATH}/dw/sim_ver"      \
                      ${STDCELL_DB_PATH} ${SRAM_DB_PATH} ]

set target_library [list "${VARIANT}_${STDCELL_CORNER}.db" \
                         "<MACRO_NAME>_${SRAM_CORNER}.db"  ]

set synthetic_library [list dw_foundation.sldb]
set synlib_wait_for_design_license [list "DesignWare-Foundation"]
set link_library [concat [concat "*" $target_library] $synthetic_library]
set symbol_library [list generic.sdb]

# used to constrain IOs in constraints
set load_lib "${VARIANT}_${STDCELL_CORNER}"
set driving_cell <NAME_OF_DRIVING_CELL>
set load_cell    <NAME_OF_LOAD_CELL>

# a NAND2 gate equivalent in this tech (for reporting purposes)
# this the area [um^2] of a Nand2 x1 gate
set NAND2_GATE_EQUIVALENT <number>

# set primary clock and reset name
set CLK_PIN clk_i
set RST_PIN rst_ni

# timing constraint in ns 
set TCK     10.0
set IN_DEL  2.0
set OUT_DEL 2.0
set DELAY   ${TCK}

# define a primary clock
create_clock ${CLK_PIN} -period ${TCK}

# assume these nets are ideal during synthesis
set_ideal_network ${CLK_PIN}
set_ideal_network ${RST_PIN}

# constrain all combinatorial paths
set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs]
set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${CLK_PIN}}] -clock ${CLK_PIN}
set_output_delay ${OUT_DEL}  [all_outputs] -clock ${CLK_PIN}

# input/output pins of stdcells are typically labelled with A,X,Y,Z or similar
set_driving_cell  -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]