Comments (3)
I'm currently working around this by supplying a TCL file in the fileset that performs the actual simulation. However, empty top level lists are not supported in a target, so I've had to create a dummy entity and architecture that do nothing, and specify this as the top level in the target. It isn't ideal, but it does work. I'm wondering if supporting an empty lop level list might be a neatest way to handle testbenches that need to be explicitly scripted like this?
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Hi,
Sorry for the lack of replies. This does sound like a tricky problem. Very annoying that they need their own setup to achieve this. Good to hear that you managed to hack your way around this at least.
I'm not sure either which would be the best way to handle this. Allowing an empty toplevel list could be one way to achieve what you're looking for. Perhaps allowing to override the simulation run command could be another. Right now I think you're in a better position than me to judge what would be the easiest and least intrusive way to support this. Also trying to think of similar issues and if this would help in those cases as well
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I'm starting to consider tools like FuseSoC or just using Edalize, and this issue with simulating Quartus IP has been the thing I'm worried about the most.
As @DHWinterWolf described, to simulate IP (even floating point entities, not just DDR3 controller IP, for example) you have to generate a simulation setup script from Quartus, open your simulator (Modelsim), then call said setup script.
@olofk Two years later, any new ideas on how to easily handle this, or new features that have already been added since the original post?
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Related Issues (20)
- Xcelium: file list HOT 1
- Modelsim missing in tools
- Support a Vivado IP-packaging flow HOT 2
- Simulating Vivado IPs (xci, bd) HOT 4
- `make_libraries_directories` on Windows fails due to `mkdir -p` HOT 3
- GHDL Support for cocotb simulation flow HOT 2
- Vars do not survive Edaflow
- Add update_compile_order to vivado workflow HOT 1
- QSys Pro 23 files are not processed correctly by the filter HOT 4
- Jinja2 issue witth edarool loader HOT 4
- Vivado flow not re-run when Verilog parameter is changed HOT 3
- Yosys: `configure_main` should check for "file_type" in fileset, or provide a default
- Incorrect toplevel name used when loading EDIF netlist in Vivado
- How to read an EDIF netlist into Vivado that isn't the toplevel?
- Not possible to fully suppress stdout in edatool API?
- Passing Verilog string parameters with quotes
- edalize/flows/edaflow.py # Yeah, I know. It's just a temporary hack HOT 1
- Symbiflow tool doesn't pass Yosys parameters when using VPR as PnR HOT 1
- Error using f4pga flow for Xilinx
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