Trouble adding a new peripheral to the system about fusesoc HOT 3 CLOSED

Hi Jeebu,

That is probably a very common thing to do, but unfortunately there isn't really any documentation for this. Here's a rough outline of the steps you should take, and don't hesitate to ask for more help. The easiest way is probably to just extend an existing system, like or1200-generic, to have something up and running quickly.
First, you have the choice of adding your core directly to the or1200-generic system or to add it as a separate core. The benefit of adding it as a separate core is that other systems can benefit from it, but you can start with putting your files directly under the or1200-generic directory to get started quicker.

1. Add the peripheral core files to or1200-generic.core
2. Add your peripheral core to data/wb_intercon.conf (this is also where you choose whick base address that your core will have in the memory map)
3. Regenerate wb_intercon.v by running ../../cores/wb_intercon/wb_intercon_gen data/wb_intercon.conf bench/verilog/wb_intercon.v
4. Add an instantiation of your core in orpsoc_top.v (the wishbone wires that your core should connect to are declared in wb_intercon.vh, which is included by orpsoc_top.v

That is roughly what needs to be done. Sorry again for the lack of documentation. We'll have to fix that

//Olof

from fusesoc.

Thanks olof, learned it after playing with the system for a couple of days time.. I just wanted to confirm that the method i followed was correct. There was a bug in the wishbone interface of my peripheral due to which data transfers failed. Now the peripheral is plugged in..
Thanks once again
Cheers
Jeebu

from fusesoc.

Hi Jeebu,

Good to hear that it worked out. For your information, there is a Wishbone master BFM (wb_bfm_master.v) in orpsoc-cores that you can use in your test bench to test the wishbone interface of your cores. We are using it in several of the memory controllers already so you can check for example the wb_intercon test bench to see how to use it.

from fusesoc.