openedf Goto Github PK

algorithm

Algorithm Source test.

basic_verilog

Must-have verilog systemverilog modules

deeplearningexamples

Deep Learning Examples

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

hdl

HDL libraries and projects

kianriscv

kianv a simple implementation of a rv32im riscv cpu and soc in verilog with firmware that runs raytracer, mandelbrot, etc.....

linux

Linux kernel source tree

linux-device-drivers-development

Linux Device Drivers Development, published by Packt

linux-on-litex-vexriscv

Linux on LiteX-VexRiscv

linux-stack

Linux driver and unix env programming

linux_driver_tutorials

This Directory contains the tutorials posted in www.embetronicx.com

lkmpg

The Linux Kernel Module Programming Guide (updated for 5.x kernels)

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

macan

risc-v soft core soc

mhome

risc-v core

no-os

Software drivers in C for systems without an operating system

nutshell

RISC-V SoC designed by students in UCAS

oh

Verilog library for ASIC and FPGA designers

open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

openc910

OpenXuantie - OpenC910 Core

opene902

OpenXuantie - OpenE902 Core

opene906

OpenXuantie - OpenE906 Core

openedf

Embedded development framework.

openhw-lib

PCB Design sources

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

practices-test

practices and test

riscv

RISC-V CPU Core (RV32IM)

riscv-tests

u-boot

"Das U-Boot" Source Tree