RAM relocatable version. about u-boot_mod HOT 34 CLOSED

Hello,

Correct me if I'm wrong. As I understand, you want a version which can be loaded to and run directly from RAM (for example, using "go" command in already running U-Boot instance), without low level initialization?

Regards!

from u-boot_mod.

Yes you did. If you use JTAG and openocd software you can do low level initialization with ar9331.cfg file.

from u-boot_mod.

OK, I will add an option to compile the code for RAM version.
Where can I find config file for AR9331, for openocd?

Regards

from u-boot_mod.

Extracting some values from u-boot source code and compiled ar9331.cfg. Trying it with carambola2 but without success. MW-AR20M & tl-wr3020 haven't JTAG pads. Very strange in AR9331 missing nTRST.

# Atheros AR9331 MIPS 24Kc SoC.
#
# this settings are taken from source of u-boot for this board
# (for PLL) file:    u-boot/board/ar7240/common/lowlevel_init.S
# (for DDR2) file:    u-boot/cpu/mips/ar7240/hornet_ddr_init.S 
#      with file:    u-boot/include/configs/ap121.h
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
set CHIPNAME ar9331
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
set TARGETNAME $CHIPNAME.cpu
target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
$TARGETNAME configure -event reset-init {
#pll initialization
mww 0xb8050008 0x00018004   
mww 0xb8050004 0x00000550
mww 0xb8050000 0x40815000
mww 0xb8050010 0x001003e8
mww 0xb8050000 0x00815000
mww 0xb8050008 0x00008000
sleep 1                         
# Setup DDR2 config and flash mapping
mww 0xb8000000 0x7fbc8cd0       
mww 0xb8000004 0x99d0e6a8

mww 0xb800008c 0xa59        
mww 0xb8000010 0x8      
mww 0xb8000090 0x0               
mww 0xb8000010 0x10         
mww 0xb8000094 0x0      
mww 0xb8000010 0x20             
mww 0xb800000c 0x0      
mww 0xb8000010 0x2           
mww 0xb8000008 0x100           
mww 0xb8000010 0x1              
mww 0xb8000010 0x8
mww 0xb8000010 0x4
mww 0xb8000010 0x4

mww 0xb8000008 0xa33
mww 0xb8000010 0x1
mww 0xb800000c 0x382
mww 0xb8000010 0x2
mww 0xb800000c 0x402
mww 0xb8000010 0x2
mww 0xb8000014 0x4270
mww 0xb800001c 0x8
mww 0xb8000020 0x9
mww 0xb8000018 0xff
}

# setup working area somewhere in RAM
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000

# serial SPI capable flash
# flash bank <driver> <base> <size> <chip_width> <bus_width>

Maybe Friday 13!!!

from u-boot_mod.

Hello netkomltd,
Can you say how you have calculated these values ​​for PLL? (I mean, are you calculated these values from source in binary mode?)
If you calculated under the standard values ​​uboot (~400MHz), then the final value(for PLL) should be:

...
mww 0xb8050000 0x00818000
...

https://forum.openwrt.org/viewtopic.php?pid=200938#p200938

Have you checked this script for OpenOCD on working capacity? (Have you tried to load any binary-file into RAM-memory and then read it again?)

Thanks,
Dmytro

from u-boot_mod.

Hello Dmytro,

I found:

      /* set SETTLE_TIME in CPU PLL */
         set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
         nop

in hornet_pll_init.S
( https://github.com/pepe2k/u-boot_mod/blob/23eda4af4cb09d14c1649e1a7f3c19b6a2b29788/u-boot/board/ar7240/ap121/hornet_pll_init.S )

and:

        #if CONFIG_40MHZ_XTAL_SUPPORT
                      // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz)
                     // REFDIV = 1
                    // RANGE = 0
                   // OUTDIV = 1
            #define CPU_PLL_CONFIG_VAL1 0x40815000
           #define CPU_PLL_CONFIG_VAL2  0x00815000

in ap121.h

(https://github.com/pepe2k/u-boot_mod/blob/8faf461987ee14e249596c132bb16c95b9b3ffcf/u-boot/include/configs/ap121.h)

Unfortunately I could not HALT AR9331 with OpenOCD.

Regards

from u-boot_mod.

I'm hacking a cheap tp-link wr840n wigh JTAG. Now, OpenOCD recognizes it with ar71xx.cfg, and nSRST works. But halt failed also. I'll try the above ar9331.cfg tomorrow.

from u-boot_mod.

Cannot halt ar9331 yet.

from u-boot_mod.

Try this:

1. Add following to ar9331.cfg :
   $TARGETNAME configure -event reset-halt-post {

   mww 0xb8050000 0x40815000
   mww 0xb8050000 0x00815000

   mww 0xb8050008 0x00008000
   }

2. Use :

poll off
reset halt

from u-boot_mod.

It didn't work with my WR840N.

I have several concerns:

• According to AR9331 datasheets, all the registers are something like 0x18XXXXXX. Why there are so many 0xb8XXXXXX in the above scripts?
• As mentioned above, the key issue is that AR9331 misses nTRST. So, how to halt it?

from u-boot_mod.

Hello yaleh,

Ad. 1 As far I know the MMU maps virtual to physical addresses. Here you can find more information: http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/mips.html

Regards

from u-boot_mod.

Hi pepe2k,

Great. Thanks.

from u-boot_mod.

With OpenOCD:

Open On-Chip Debugger 0.7.0 (2013-06-22-17:01)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
131072
adapter speed: 100 kHz
Info : J-Link initialization started / target CPU reset initiated
Info : J-Link ARM V8 compiled Jun 19 2012 11:29:30
Info : J-Link caps 0xb9ff7bbf
Info : J-Link hw version 80000
Info : J-Link hw type J-Link
Info : J-Link max mem block 9320
Info : J-Link configuration
Info : USB-Address: 0x0
Info : Kickstart power on JTAG-pin 19: 0xffffffff
Info : Vref = 3.351 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 0 TRST = 0
Info : J-Link JTAG Interface ready
Info : clock speed 100 kHz
Info : JTAG tap: ar9331.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000, ver: 0x0)
Info : accepting 'telnet' connection from 4444
Info : JTAG tap: ar9331.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000, ver: 0x0)
Info : Halt timed out, wake up GDB.
Error: timed out while waiting for target halted
TARGET: ar9331.cpu - Not halted

But with urjtag, it seems worse:

UrJTAG 0.10 #2007
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable jlink
J-Link initial read failed, don't worry (result=0)
Vref = 3.351 TCK=1 TDI=0 TDO=0 TMS=0 TRES=1 TRST=1
J-Link JTAG Interface ready
jtag> detect
warning: TDO seems to be stuck at 0

from u-boot_mod.

Today i was able to launch jtag on ar9331. The are two trick was needed on my MR3010 board:

• disable flash. uboot reconfigured this pins from jtag to gpio
• gpio11 should be up on power on. On my boar the SW2 switch is connected to this pin. so just hold it on poweron
• no special config is needed for openocd. well at least to launch ejtag
• if you need ram, you will need to configure it per jtag.

from u-boot_mod.

I was too lazy and tested (without thinking) sequence from netkomltd comment. Suddenly it isn't working...
Uff it will take some time to figure it out, unless some one has some suggestions ;)

from u-boot_mod.

Ram problem is solved too. I gathered some information here:
http://wikidevi.com/wiki/TP-LINK_TL-MR3020#JTAG

from u-boot_mod.

Hi olerem,
TL-MR3020 has a DDR1 on board. Please insert correct comment in WIKI.
Regards.

from u-boot_mod.

@netkomltd, thx. corrected.

from u-boot_mod.

Can try GPIO1 (R2 tie to GND) on bootstrap to isolate spi flash without cutting CS.

from u-boot_mod.

hi. friends. I have try openocd on centos. want to debug ar9331 via jlink. but I got these errors

Info : J-Link initialization started / target CPU reset initiated
Info : J-Link ARM V8 compiled Nov 25 2013 19:20:08
Info : J-Link caps 0xb9ff7bbf
Info : J-Link hw version 80000
Info : J-Link hw type J-Link
Info : J-Link max mem block 9296
Info : J-Link configuration
Info : USB-Address: 0x0
Info : Kickstart power on JTAG-pin 19: 0xffffffff
Info : Vref = 3.300 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 0 TRST = 0
Info : J-Link JTAG Interface ready
Info : clock speed 5 kHz
Info : TAP ar9331.cpu does not have IDCODE
Warn : JTAG tap: ar9331.cpu UNEXPECTED: 0x00000000 (mfg: 0x000, part: 0x0000, ver: 0x0)
Error: JTAG tap: ar9331.cpu expected 1 of 1: 0x00000001 (mfg: 0x000, part: 0x0000, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Error: ar9331.cpu: IR capture error; saw 0x11 not 0x01
Warn : Bypassing JTAG setup events due to errors

could you kindly give me some adivces. thanks very much

from u-boot_mod.

i tried all my super power to remotely figure out what is your problem, but suddenly it was not enough. So lets try less scientific method. First i ask you, what you did to get it?

from u-boot_mod.

Hi, friend. thanks your help.

I used a Jlink and connect the JTCK TDI TDO TMS GND and 5V to a ar9331 device. I have check the lines. it should nothing to pull down or up but connected all lines direct to ar9331 chipset.

when I run openocd -f scripts/interface/jlink.cfg -f scripts/target/ar9331.cfg on centos. I got these errors. but sometimes the ar9331 IOs will get a confused status. I pinout all gpios to leds. and confused lighting.

can you help me? thanks again.

from u-boot_mod.

Did you pulled up GPIO11?

from u-boot_mod.

hi. thanks for you msg again.

I keep the GPIO1 to GND. and get these info from UART

VID=0xcf3,PID=0x9330
iManufacturer=0x10,iProduct=0x20,iSerialNumber=0x30
bMaxPower=0xfa
-> COLD_START
bUSBPhyBias=0x3
RUN

Did I enter debug mode?

from u-boot_mod.

I'm not sure if you can read, or understand me.

from u-boot_mod.

I have try GPIO11 to pull up when power on. got the same errors.

I try openocd with libusb win32 on win7.

got these errors.

Info : J-Link initialization started / target CPU reset initiated
Error: J-Link command 0xde failed (o)
Error: J-Link command 0xdc failed (o)
Error: J-Link command 0x01 failed (o)
Error: J-Link command EMU_CMD_VERSION failed (o)

from u-boot_mod.

Did you tested your jtag configuration with other devices?

from u-boot_mod.

Thanks friend.

Let me have a try

------------------ Original ------------------
From: "Oleksij Rempel"[email protected];
Date: Tue, Jun 10, 2014 00:55 AM
To: "pepe2k/u-boot_mod"[email protected];
Cc: "ooioe"[email protected];
Subject: Re: [u-boot_mod] RAM relocatable version. (#2)

I'm not sure if you can read, or understand me.

—
Reply to this email directly or view it on GitHub.

from u-boot_mod.

I have reset all softwares,driver . and let IO1 to GND, IO11 to 3V3. and get these info

Info : J-Link initialization started / target CPU reset initiated
Info : J-Link ARM V8 compiled Nov 25 2013 19:20:08
Info : J-Link caps 0xb9ff7bbf
Info : J-Link hw version 80000
Info : J-Link hw type J-Link
Info : J-Link max mem block 9296
Info : J-Link configuration
Info : USB-Address: 0x0
Info : Kickstart power on JTAG-pin 19: 0xffffffff
Info : Vref = 3.306 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 0 TRST = 0
Info : J-Link JTAG Interface ready
Info : clock speed 100 kHz
Info : JTAG tap: ar9331.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000, ver: 0x0)

seem something improve. but halt here. any advice? thanks very much

from u-boot_mod.

CPU was started in debug mode, It is correct. I do not understand your question.

from u-boot_mod.

thanks your replay. But stop this line. I can't get anything more

------------------ Original ------------------
From: "Oleksij Rempel"[email protected];
Date: Wed, Jun 11, 2014 08:23 PM
To: "pepe2k/u-boot_mod"[email protected];
Cc: "ooioe"[email protected];
Subject: Re: [u-boot_mod] RAM relocatable version. (#2)

CPU was started in debug mode, It is correct. I do not understand your question.

—
Reply to this email directly or view it on GitHub.

from u-boot_mod.

you need to connect to openocd by using "telnet localhost 4444"

from u-boot_mod.

LOL... I been misinformed. thanks very much..

------------------ Original ------------------
From: "Oleksij Rempel"[email protected];
Date: Wed, Jun 11, 2014 08:39 PM
To: "pepe2k/u-boot_mod"[email protected];
Cc: "ooioe"[email protected];
Subject: Re: [u-boot_mod] RAM relocatable version. (#2)

you need to connect to openocd by using "telnet localhost 4444"

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Reply to this email directly or view it on GitHub.

from u-boot_mod.

RAM version is available: 297d08d

from u-boot_mod.