Comments (6)
leonardt
commented on July 30, 2024
This seems okay to me, @phanrahan @rdaly525 any thoughts?
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rdaly525
commented on July 30, 2024
I would be fine with this change. I think it would be good to be consistent with what other libraries do. I think that ice40 also has this behavior but I am not positive.
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phanrahan
commented on July 30, 2024
Having resets have priority makes sense to me.
We should double-check the FPGA backends to make sure they implement this semantics if we make the change.
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Kuree
commented on July 30, 2024
Do you know when it's going to be fixed? I have to put a lot of hacks in my PnR to make reset signal reach the registers first before the enable signal during the configuration.
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leonardt
commented on July 30, 2024
I can have this fix done by tomorrow
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leonardt
commented on July 30, 2024
Change is now in master, will be available in release v0.1.15 soon. Can you guys try it out and let me know if it works as expected?
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Related Issues (20)
- Remove generated wrappers from coreir modules HOT 5
- Register should work with the _type parameter
- mantle Register not working HOT 2
- Bug In Mantle/CoreIR Simulation Of RAM HOT 2
- Unify coreir's commonlib and mantle
- Add logical and, or, not functions
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- [primitives] generalizing width parameter interface to a type parameter interface HOT 2
- Cannot wire Mux2 HOT 6
- Regression with latest magma release HOT 2
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