Comments (13)
Did you install a YAML parser? Use pip
to snag one. I think I used pyyaml
.
Also, which version of Python are you using?
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I ran manage.sh update_dev_packages
which installed the required dependencies I think? In anycase, pyyaml is already installed.
Python 3.7.2
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Well dang. I get the same result. @antoniovazquezblanco ? I'm out of time today but can look at this tomorrow if Antonio doesn't answer.
Can you run other scripts? The other Harwin one doesn't work for me but conn_jst_eh_tht_side.py
in the Connector_JST folder does.
I'm also on 3.7.2.
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Yup, that one worked, although warnings about safe load, and also
Invalid -W option ignored: invalid module name: 'yaml'
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#320 for when things are semi-functional.
Dunno how I feel about the detailed silk screen... also, Samtec offers 4 pin lengths, also unsure how to handle. Perhaps a graphical display with 4 lines indicating the different offsets? But keep the traditional/most common depth?
Quick example:
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Fixed both Harwin script issues at #322.
On pin length, I have two proposals. Our library is big enough to support many footprints, but since it's also general-purpose I'm inclined to support the greatest number of footprints possible.
- Just make the one you want.
- Build the longest one and then shorter ones will fit inside. This is the lowest common denominator approach. I favor this for our library if it works for you.
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Sweet, that'll get me tinkering.
My issue with option 2 is that I bet 99% will use the standard length. Building the longer one will waste space for most people designs.
Another thought:
This connector would very likely be at the edge of the board, or if not, it would need to have quite a bit of space left in front to allow for plugging in of the header.
The pin outline could reflect the standard pin length, but the courtyard could reflect the longest pin length? For something overhanging the edge of the board, the courtyard would have no ill effect. Of course it would violate KLC, which might bring us back to option 1 which is the one I want :)
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Okay, so I had an issue with the pin 1 silkscreen.
I changed a few lines, from 6.775 to 6.98
s_pin1 = [
{'x': -6.98+padsize[0]/2-(2.5/2+configuration['silk_pad_clearance']+configuration['silk_line_width']), 'y': -(pitch*(pinnum-1))/2},
{'x': -6.98+padsize[0]/2-(2.5/2+configuration['silk_pad_clearance']+configuration['silk_line_width']), 'y': -(pitch*(pinnum-1))/2-1/2-configuration['silk_line_width']-configuration['silk_pad_clearance']},
{'x': -6.98+padsize[0]/2, 'y': -(pitch*(pinnum-1))/2-1/2-configuration['silk_line_width']-configuration['silk_pad_clearance']},
]
Looking better. That number 6.775 is everywhere. And then I noticed the silkscreen for the pins is off as well.
So it leads me to believe perhaps I need to be fixing it elsewhere? Or is this just part of the game?
I do notice a silkscreen pad offset, but can't find that configured anywhere, and perhaps I don't want to touch that.
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A few tweaks, latest commit has this coming out the other end
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Thoughts on this? Should I submit a PR for continued discussion in kicad-footprints ?
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The courtyard should match the footprint.
Good catches on the silkscreen. Magic numbers are no good, especially if it's used all over the code. You will want to keep 0.12mm or more clearance from pads to silk, which turns into 0.18mm since you need to consider half of the silk line width (or the endcap radius). If there is a silkscreen pad offset not being used, it seems like a good variable name so put it to use or remove it so nobody else is confused in the future.
Script quality can vary, and the framework sometimes changes, so it may take a bit of work to start with an existing script and end up with something nice. Great work!
The screenshots above look OK, but in this case a footprint PR with all the parts to view in KiCad and a script PR will be the best way to get this reviewed and merged.
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I'll get a PR going.
RE: Courtyard, I followed KLC for a connector. One might argue that the pin-side should be even bigger to allow mating?
Connectors should have a clearance of 0.5mm, in addition to the clearance required for mating of connector
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Related Issues (20)
- Abstract settings from IPC-compliant scripts
- PadArray exclude pad only works with pure numerical initial pin. HOT 3
- Some footprints are generated by the IPC scripts but do not appear in the footprint repo HOT 1
- Crystals generation scripts inconsistency
- Molex KK 254 series drill size too big (conn_molex_kk_254_tht_top.py) HOT 12
- yaml file for mounting holes? HOT 1
- Extratexts generate a line in the footprint even if the string is empty
- Make manage.sh into python script
- pad clearance HOT 3
- Define center pad paste pad grid HOT 3
- documentation for footprint generation, fix pad size? HOT 4
- deprecate 'at' keyword
- SMA footprint
- Similar script directory names HOT 2
- Error in yaml HOT 8
- Footprint generator for AC/DC, DC/DC converters HOT 4
- GitLab migration HOT 1
- Reproducable builds, Basic CI HOT 3
- Offset in Pad not taken into account
- Commandline paramters of ipc_* generators are not described well
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