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powerhuafei's Projects

chisel icon chisel

Chisel: A Modern Hardware Design Language

eep-tpu-sdk icon eep-tpu-sdk

Includes compiler and library for EEPTPU, you can develop your own application and run it on your board with EEPTPU IP.

firesim-nvdla icon firesim-nvdla

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

free-tpu icon free-tpu

Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

free-tpu-v3plus-for-fpga icon free-tpu-v3plus-for-fpga

FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference

learning-nvdla-notes icon learning-nvdla-notes

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

mnist-nnet-hls-zynq7020-fpga icon mnist-nnet-hls-zynq7020-fpga

to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj accelerate code in FPGA,and implacement in block design and with SDK app......

pocl icon pocl

a clone of POCL that includes RISC-V newlib devices support and Vortex

sodla icon sodla

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

tengine icon tengine

Tengine is a lite, high performance, modular inference engine for embedded device

v831-npu icon v831-npu

全志科技 V831 NPU逆向工程 Reverse engineering the V831 npu

zynq-nvdla icon zynq-nvdla

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

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