programmable-logic-tools Goto Github PK
Name: Programmable Logic Tools
Type: Organization
Name: Programmable Logic Tools
Type: Organization
Third-party software tools for Altera MAX CPLDs
Third-party bitstream documentation for Altera MAX7000 CPLDs
Inofficial KiCad 5 schematic for Atmel's ATDH1150USB(-K) JTAG debugger for CPLDs
VHDL syntax highlighting definition for the Bluefish editor
Flashes FPGA bitmaps onto Lattice iCE40 evaluation board through the onboard FTDI-2232H
Very slightly modified version of Alessandro Zummo's GALasm 2.1, for programming GAL devices
Portable GAL Assembler
Verilog models for the GAL22V10 and select PAL devices.
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
FPGA-based tool to analyze and debug JTAG connections
Lattice XP2 Standard evaluation board Diamond playground
A library of basic building blocks for programmable logic designs
Python libraries to help writing pin constraints files for programmable logic projects
Technical documentation required for understanding how Xilinx Spartan FPGAs work and must be programmed
Inofficial mirror of Tachyon DA's CVC Verilog to Executable compiler
Inofficial KiCad 5 schematic for Terasic's USB-Blaster (JTAG debugger) for Altera CPLDs and FPGAs
Eclipse Verilog/VHDL Editor - a fork of the SourceForge repository
A little JavaScript magic to convert VHDL source into a neat block diagram
Reverse engineering the XC2064 FPGA
Yosys Open SYnthesis Suite
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