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ahb-systemverilog

awesome-git-hooks

😎 A collection of awesome Git Hooks

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

design-verification

Course content for the University of Bristol Design Verification course.

hust-lab

Labs for Computer Science - c, asm, data structure, csapp, hsi, matlab, digital logic, verilog, compilers, operating systems

imperas-riscv-tests

learnopengl

Code repository of all OpenGL chapters from the book and its accompanying website https://learnopengl.com

library-management-system-cpp

lungcancer_keras

modern-opengl-tutorials

mult-dut-parl-stim

Multiple DUT with parallel stimulus

openram

An open-source static random access memory (SRAM) compiler.

project-geofencer

pure-bash-bible

📖 A collection of pure bash alternatives to external processes.

python

All Algorithms implemented in Python

python4rtlverification

pythondatasciencehandbook

Python Data Science Handbook: full text in Jupyter Notebooks

pyuvm

The UVM written in Python

riscv-dv

Random instruction generator for RISC-V processor verification

system-bus-design-verilog

This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

systemverilog-constructs

Examples of unions, interfaces, and assertions in SystemVerilog

transformers

🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.

uvm-examples

UVM examples and projects

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

uvmreference

Reference examples and short projects using UVM Methodology

vba

Code Blocks relating to everything VBA

vscode-tips-and-tricks

Collection of helpful tips and tricks for VS Code.