Report about bme351 HOT 6 CLOSED

y433wu@ecetesla3:~/ece327/BME351/kirsch_proj$ uw-synth --opt kirsch.uwp
    INFO: Starting PRECISION_RTL for logic synthesis
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
       INFO: generic-gate       netlist         written to uw_tmp/kirsch_gate.vhd
    INFO: generic-gate       area estimate   written to RPT/area_gate.rpt
    INFO: logic-synthesis    netlist         written to uw_tmp/kirsch_logic.vhd
    INFO: logic-synthesis    area estimate   written to RPT/area_logic.rpt
    INFO: logic-synthesis    timing estimate written to RPT/timing_logic.rpt
    INFO: --------------------------------------------------------------------------------
    INFO: AREA = 231 cells (231 luts, 169 regs) (estimated by logic-synthesis)
    INFO: Speed on Stratix IV = 186 MHz,  5.37 ns (estimated by logic-synthesis)
    INFO: --------------------------------------------------------------------------------
    INFO: CRITICAL PATHS (slowest 5 paths, estimated by logic synthesis)
    INFO: ..........Delays.........
    INFO:  Total  Datapath  Routing          Source              Dest
    INFO: ------  --------  -------   --------------------  ---------------------
    INFO:   5.37     5.22     0.15    h(1)                  reg1_val(9)/d
    INFO:   5.32     5.18     0.15    d(1)                  reg1_val(9)/d
    INFO:   5.32     5.17     0.15    a(0)                  reg1_val(9)/d
    INFO:   5.32     5.17     0.15    h(0)                  reg1_val(9)/d
    INFO:   5.29     5.15     0.15    h(5)                  reg1_val(9)/d
    INFO:
    INFO: OPTIMALITY
    INFO:              ..............latency...............
    INFO:              =<  8cyc   9cyc  10cyc   11cyc   12cyc
    INFO: optimality   =   805    765    728     692     659
    INFO: latency                 = 8
    INFO: optimality with latency = 805
    INFO:
    INFO: ***********************************************
    INFO: *
    INFO: * uw-synth to STRATIXIV was successful
    INFO: * log file stored in LOG/uw-synth.log
    INFO: *
    INFO: ***********************************************

 y433wu@ecetesla3:~/ece327/BME351/kirsch_proj$ uw-synth --chip kirsch.uwp
    INFO: Starting PRECISION_RTL for logic synthesis
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
       INFO: generic-gate       netlist         written to uw_tmp/kirsch_gate.vhd
    INFO: generic-gate       area estimate   written to RPT/area_gate.rpt
    INFO: logic-synthesis    netlist         written to uw_tmp/kirsch_logic.vhd
    INFO: logic-synthesis    area estimate   written to RPT/area_logic.rpt
    INFO: logic-synthesis    timing estimate written to RPT/timing_logic.rpt
    INFO: --------------------------------------------------------------------------------
    INFO: AREA = 344 cells (344 luts, 165 regs) (estimated by logic-synthesis)
    INFO: Speed on Max 10 = 101 MHz,  9.85 ns (estimated by logic-synthesis)
    INFO: --------------------------------------------------------------------------------
    INFO: CRITICAL PATHS (slowest 5 paths, estimated by logic synthesis)
    INFO: ..........Delays.........
    INFO:  Total  Datapath  Routing          Source              Dest
    INFO: ------  --------  -------   --------------------  ---------------------
    INFO:   9.85     9.58     0.27    cycles(1)             reg3(13)/d
    INFO:   9.85     9.58     0.27    cycles(0)             reg3(13)/d
    INFO:   9.68     9.41     0.27    cycles(2)             reg3(13)/d
    INFO:   9.10     8.83     0.27    cycles(3)             reg3(13)/d
    INFO:   7.98     7.71     0.27    f(0)                  reg3(13)/d
    INFO: Starting QUARTUS for physical synthesis
    INFO: map... fit... tan... asm... eda...
     INFO: generic-gate       netlist         written to uw_tmp/kirsch_gate.vhd
    INFO: generic-gate       area estimate   written to RPT/area_gate.rpt
    INFO: logic-synthesis    netlist         written to uw_tmp/kirsch_logic.vhd
    INFO: logic-synthesis    area estimate   written to RPT/area_logic.rpt
    INFO: logic-synthesis    timing estimate written to RPT/timing_logic.rpt
    INFO: chip               netlist         written to uw_tmp/kirsch_chip.vhd
    INFO: chip               area estimate   written to RPT/area_chip.rpt
    INFO:
    INFO: ***********************************************
    INFO: *
    INFO: * uw-synth to lstep was successful
    INFO: * log file stored in LOG/uw-synth.log
    INFO: *
    INFO: ***********************************************

   INFO: Starting PRECISION_RTL for logic synthesis
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
INFO: Analyzing "util.vhd"
INFO: Analyzing "kirsch_synth_pkg.vhd"
INFO: Analyzing "mem.vhd"
INFO: Analyzing "kirsch.vhd"
       INFO: generic-gate       netlist         written to uw_tmp/kirsch_gate.vhd
    INFO: generic-gate       area estimate   written to RPT/area_gate.rpt
    INFO: logic-synthesis    netlist         written to uw_tmp/kirsch_logic.vhd
    INFO: logic-synthesis    area estimate   written to RPT/area_logic.rpt
    INFO: logic-synthesis    timing estimate written to RPT/timing_logic.rpt
    INFO: --------------------------------------------------------------------------------
    INFO: AREA = 224 cells (224 luts, 167 regs) (estimated by logic-synthesis)
    INFO: Speed on Stratix IV = 200 MHz,  4.99 ns (estimated by logic-synthesis)
    INFO: --------------------------------------------------------------------------------
    INFO: CRITICAL PATHS (slowest 5 paths, estimated by logic synthesis)
    INFO: ..........Delays.........
    INFO:  Total  Datapath  Routing          Source              Dest
    INFO: ------  --------  -------   --------------------  ---------------------
    INFO:   4.99     4.84     0.15    cycles(1)             reg3(13)/d
    INFO:   4.97     4.82     0.15    c(0)                  reg3(13)/d
    INFO:   4.96     4.81     0.15    e(0)                  reg3(13)/d
    INFO:   4.95     4.80     0.15    b(0)                  reg3(13)/d
    INFO:   4.94     4.79     0.15    d(0)                  reg3(13)/d
    INFO:
    INFO: OPTIMALITY
    INFO:              ..............latency...............
    INFO:              =<  8cyc   9cyc  10cyc   11cyc   12cyc
    INFO: optimality   =   892    848    807     767     730
    INFO: latency                 = 8
    INFO: optimality with latency = 892
    INFO:
    INFO: ***********************************************
    INFO: *
    INFO: * uw-synth to STRATIXIV was successful
    INFO: * log file stored in LOG/uw-synth.log
    INFO: *
    INFO: ***********************************************

y433wu@ecetesla3:~/ece327/BME351/kirsch_proj$ uw-sim --logic --timing --nogui kirsch.uwp
uw-sim /home/ece327/bin/uw-sim --logic --timing --nogui kirsch.uwp
    INFO: Using testbench        : kirsch_tb
    INFO: Using design entity    : kirsch
    INFO: Using simulation script: kirsch_tb.sim


# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.kirsch_synth_pkg(body)
# Loading work.file_pkg(body)
# Loading work.string_pkg(body)
# Loading work.kirsch_unsynth_pkg(body)
# Loading work.util(body)
# Loading work.state_pkg
# Loading work.kirsch_tb(main)#1
# Loading work.kirsch(logic_shim)#1
# Loading work.kirsch_logic(main)#1
# Loading work.ram_dq_8_0(implementation)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.ram_dq_8_1(implementation)#1
# Loading work.ram_dq_8_2(implementation)#1
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# LOGIC_MODE
# False
# bubbles=3
# runtime=5250880
# ** Note: XXXXXXXXXXXX reading image from tests/test1.txt
# ** Note: latency begin wait
#    Time: 41302 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41320 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41340 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41360 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41380 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41400 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41420 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41440 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41460 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency waiting
#    Time: 41480 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: latency = 8
#    Time: 41480 ns  Iteration: 1  Instance: /kirsch_tb
# ** Note: XXXXXXXXXXXX sent image
#    Time: 5243002 ns  Iteration: 0  Instance: /kirsch_tb
# ** Note: XXXXXXXXXXXX got image
#    Time: 5243160 ns  Iteration: 1  Instance: /kirsch_tb