Comments (2)
Please find attached the output of cache-info with and without the nosmt option, when cpuinfo is built with debug log level.
cache-info.nosmt.txt
cache-info.smt.txt
from cpuinfo.
Looking at the x86 logic (I'm horribly unfamiliar with it, so bear with me here :)), it looks like we'd only accidentally generate N caches if we assigned them each different L1I IDs. Digging through the code paths here, I don't see anywhere we would accidentally mark the same ID as different IDs, so that leads me to believe that our l1i_id calculation fails somehow.
# How we calculate the apic_bits for each cache in `cpuinfo_x86_decode_cache_properties`.
const uint32_t cores = 1 + ((regs.eax >> 14) & UINT32_C(0x00000FFF));
const uint32_t apic_bits = bit_length(cores);
...
# How we later mask to acquire the L1I ID.
const uint32_t apic_id = linux_processors[i].apic_id;
const uint32_t l1i_id = apic_id & ~bit_mask(x86_processor.cache.l1i.apic_bits);
I'd hazard a guess that this means either:
- The
apic_id
is wrong for all processors with 'nosmt' enabled? - The
apic_bits
is wrong for all caches with 'nosmt' enabled?
from cpuinfo.
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from cpuinfo.