qiyuzhou Goto Github PK
Name: Qiyu Z
Type: User
Qiyu Z's Projects
4-way-set-associative-cache-verilog
Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
4way-cache
Verilog cache implementation of 4-way FIFO 16k Cache
hellorepo
just try
mem_cache
A memory cache implemented in Verilog
modica-sram
Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and characterization of inverters for different supply voltages (VDD) and temperatures. It also includes HSPICE decks for the characterization of the 6-transistor SRAM cell for different transistor ratios, and the SRAM read and write circuitry. Co-designed and co-developed the SRAM using schematic entry in Cadence Virtuoso. Performed functional and timing verification by simulating extracted SPICE netlist in NanoSim.
sram_verilog
not on board, using reg
uvm-testbench-tutorial-simple-adder
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
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