rajumachupalli Goto Github PK

accelergy-timeloop-infrastructure

Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop

adaption

An adapted version of the original caffe deep learning library to support training, finetuning and testing of convolutional neural networks with limited numerical precision of weights and activations

aichip

Aiming at an AI Chip based on RISC-V and NVDLA.

capturethebug_riscv_hackthon

This repo contains the materials gathered as Hackathon progress.

convnet-burden

Memory consumption and FLOP count estimates for convnets

core-v-mcu-devkit

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

deep-learning-resources

Getting Started with Deep learning resources

dnnweaver2

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

hls4ml

Machine learning in FPGAs using HLS

image_extract

This repo is to extract contents from the input image.

imagenet-datasets-downloader

ImageNet dataset downloader. Creates a custom dataset by specifying the required number of classes and images in a class.

iterativemac_carnival

The project is a part of AI generated chip design contest. Designing an Iterative MAC based DNN accelerator for inference which can also train the models using same resources.

linux-xlnx

The official Linux kernel from Xilinx

lottery-ticket-hypothesis

A reimplementation of "The Lottery Ticket Hypothesis" (Frankle and Carbin) on MNIST.

machine_learning_hardware

Paper Collection for Machine Learning Hardware

marmot_asic

Twin SOC based on carvel and rocket-chip. a project from MPW-5 shuttels

neural-networks-on-silicon

This is a collection of works on neural networks and neural accelerators.

openlane_training_vsd

As a part of open lane project training from vsdworkshop

openroad_flow_script_iitg

It is a part of workshop organized by NINE labs at IITG for students to understand the Open Roads Flow Script (ORFS)s.

openxla

papers

Summaries of machine learning papers

tcl_workshop

TCL workshop: Learning TCL scripting through designing an UI for synthesis and timing analysis using Yosys and OpenTimer tools

verilog_basics

Verilog basics for quick review

vlsi-fundamentals-a-practical-approach-education-kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.