Comments (4)
Just to know, was there any problem with the VHDL design?
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Sorry for the delay.
How are you getting the power report?
I am using the same ASIC synthesis tool and configuration I used in the original paper to obtain the results shown in the /figsdirectory (Synopsys DC, with 45 nm TSMC library).
The area, delay and power results follow the expected trend: the P(32,0) multiplier requires more resources compared to P(32,2) unit. This is because in the 0-exponent case the fraction field will be 2 bits larger, and thus the hardware multiplier (which is the most power-hungry submodule) will be larger as well.
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Thank you,
So I need to check my results more.
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