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The project aims at developing a DDS based function generator to generate a sine wave frequency sweep in the range of 390 kHz. For doing this the FPGA will be used to run the dds algorithm and then a DAC and a reconstruction filter will be interfaced of the required order to have a final output on the CRO.
DDS frequency generator for the Icestick FPGA board
Target Device: xc3s500e-4pq208 Xilinx Spartan 3E EXCD-1开发板
FPGA UART entity written in VHDL
fpga_dds
Sharing the joy of robot programming in the spirit of open source
Several image/video enhancement methods, implemented by Java, to tackle common tasks, like dehazing, denoising, backscatter removal, low illuminance enhancement, featuring, smoothing and etc.
Lightweight UART core in VHDL
UART core for FPGA written in VHDL
Simple UART controller for FPGA written in VHDL
VHDL : RS232 TX/RX - FPGA ( used for teaching full ppt included )
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