Comments (2)
I'm not sure what I'm looking at in the above graphs. . . SCK and SDO both from the SPI master? In principle, it looks right; the SDO is aligned with the rising edge of the clock in one mode and the falling edge of the clock in the other mode. But do you have an SPI slave in the testbench that can also be put in mode 0 or mode 1? The modes of master and slave have to match, or else yes, there will definitely be race conditions and misinterpretation of data.
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yes, sck and sdo are from the SPI master.
yes the slave works with different modes.
The mode that align with rising edge is functionally right only the last pose edge reads 1 at this example. However the mode that aligns with negative edge reads 1 at edges number 6 and 7 (counting from 0)
Here are some other trials sending byte in this mode to provide more details about the shift between clock driving and data sending.
try sending 0x00 but it sends 0x1
try sending 0x7F but it sends 0xFF
try sending 0x02 but it sends 0x05
try sending 0x03 but it sends 0x07
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Related Issues (15)
- Select out of bounds on signal `gpio_dat_o[*]` HOT 8
- GPIO vector [0] and [43] input are shorted with the output HOT 4
- Flashing isn't working with vcs HOT 1
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- Hold violation on path with start point `gpio_in[38]` (clock) HOT 4
- Housekeeping reset register doesn't function HOT 2
- Wrong dimensions for `gpio_analog_pol[33]` in template def HOT 3
- Missing pins in template def HOT 4
- RTL changes needed for iverilog v12 HOT 1
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- counter interrupts HOT 3
- Needs multiple power supply connections
- Need reset synchronization HOT 1
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