Can't extract resistor about magic HOT 6 CLOSED

I now realize that my labels should be ports, which I found out by reading archived emails and ctrl-F searching for "extresist". My problem doesn't exist anymore, thanks for keeping old emails in the website.

from magic.

I really need to update some of the tutorials with newer information. The original extresist would only extract nets between transistor terminals, so a resistor ending in a label would be completely ignored. I did not attempt to mess with that general principle of ignoring dangling wires going to nowhere, but I did add the capability to treat a port as a driver or receiver point.

I'm glad the email archive was useful (even if the documentation was lacking)!

from magic.

Something still bothers me... the behavior is not really consistent as I thought so. I created another simple circuit with ports and "extresist" crashed everytime I ran it, but when I created a complete circuit, with VDD, GND, NMOS and PMOS, it worked fine with the ports. I feel that for educational purposes at least, being able to create a model of a single line of polysilicon should be possible, instead of only "complete circuits". Here's a print of the minimal setup I needed for extresist not crashing with ports, which makes sense with your description of looking for wires between transistors. While trying to understand it earlier I figured it could be an actual project decision.

A few more things bugging my head:

• The tutorial file (tut8r.mag) doesn't use any ports whatsoever and it still extracts resistances as I expected, without segmentation faults.

• "ext2sim" running in "example.ext" sometimes creates "example.ext.sim" and sometimes "example.sim" (same thing happens with .nodes whenever labels are on).

By the way, your initiative is amazing, Tim, and I really hope I could learn the most out of Magic so I can contribute with it as well someday. Thank you very much.

from magic.

If your layout crashes extresist, please post the layout file, as I would like to use it to debug the (first) problem. I am inclined not to worry about the ".ext.sim" problem because my goal (which I hope to get around to soon, because it is becoming a high priority) is to get rid of the dependence of "extresist" on the .sim files completely. The .ext files have all the needed information, and the .sim files are missing some needed information. This goal would also simplify the full-parasitic extraction to just a few commands.

from magic.

Here are the files of a layout that crashes extresist.

An interesting thing about it: I made the substrate a port so I could connect it anyway I'd prefer in spice, but (even though extresist crashes), the ext2spice output doesn't present the body connection in PIN 4 of the FET model, but it uses a "Gnd" that I never included.

.option scale=1u
.subckt crashte source drain in body
M1000 drain in source Gnd nfet w=5 l=2
+ ad=30 pd=22 as=30 ps=22
C0 in Gnd 11.27fF
.ends

crash.zip

from magic.

The "Gnd" connection is a limitation of the SCMOS technology files. . . they are old and do not have support for some things like substrate extraction that I added to Magic. But it is also a limitation of the .sim format, which has no concept of a substrate at all (all .sim transistors are 3-terminal devices). Which is why I want to remove the dependence on the .sim format.

from magic.