russellfriesenhahn Goto Github PK

alpha

avsdbgp_3v3_sky130_v2

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

caravel-lite

caravel_user_project

https://caravel-user-project.readthedocs.io

clear

docker-files

docker_open-src-cvc

Dockerfile for OSS CVC verilog simulator

gf180-mpw2

Programmable 10-tap FIR filter with configurable thresholding and snapshoting capabilities

gf180-russell

Matt Venn's VGA Clock w/ SPI control and an LFSR-based scrambler

ice40

Lattice iCE40 FPGA experiments - Work in progress

learn-sky130

Learning to do things with the Skywater 130nm process

lmac_core3

Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps

multi_project_tools

open-src-cvc

Mirror of tachyon-da cvc Verilog simulator

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane-sky130-workshop

Advanced Physical Design workshop using OpenLANE/Sky130

openlane_summary

opensourcephydesign

SOC Physical Design Workshop with Open Source Tools

pandoc-examples

prefix_adders

Prefix adder generators for Verilog

russellfriesenhahn

Config files for my GitHub profile.

sphinx-wavedrom

A sphinx extension that allows including wavedrom diagrams by using its text-based representation

spi

stc0

Test Chip 0 that implements an FFT butterfly and interfaces to stream data.

stc0_caravel_user_project

style-guides

lowRISC Style Guides

vga-clock

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

vsdmixedsignalflow

This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.