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  • 👋 Hi, I’m Mark Sears
  • I'm a PhD student at UT Dallas studying FPGA implementation, tools, and algorithms.
  • Right now I'm working on implementing a placement algorithm on the Xilinx Versal architecture.
  • You can email me at [email protected]

searsm8's Projects

aieplace icon aieplace

Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.

channel_routing icon channel_routing

Algorithms which solve the channel routing and switchbox routing physical design problems.

dse icon dse

Scripts to perform Design Space Exploration (DSE) using CyberWorkBench High-Level Synthesis tool

fm_partitioning icon fm_partitioning

Program which implements Fiduccia–Mattheyses partitioning algorithm

ispd_2020 icon ispd_2020

Code for the International Symposium of Physical Design (ISPD) 2020 Contest Objective is to provide heuristic solutions for Cerebras' Wafer Scale Engine (WSE)

lenet icon lenet

Simple implementation of LeNet using PyTorch

mlir-aie icon mlir-aie

An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.

msdap icon msdap

Verilog project to implement an ASIC chip from specification to tape out. Performs audio filtering, known as the Mini Stereo Digital Audio Processor (MSDAP)

openroad icon openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

phdlog icon phdlog

Day-to-day log files of my PhD research

searsm8 icon searsm8

Config files for my GitHub profile.

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