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A DDR3 memory controller in Verilog for various FPGAs
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
DDR4 Simulation Project in System Verilog
两路摄像头,pcie上位机传输
DDR2 mem controller for Digilent Genesys Board
Real-Time Image Processing for ASIC/FGPA
基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
LPDDR2 Model
USB2.0 Device Controller IP Core
PCI Express ® Base Specification Revision 3.0
PCIE 5.0 Graduation project (Verification Team) under supervision of Mentor Graphics
fpga PCIE测速,采用riffa架构
Wavious DDR (WDDR) Physical interface (PHY) Hardware
xkISP:Xinkai ISP IP Core (HLS)
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.