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sv_axis_median_3x3

Median filtrer size of 3x3 for AXI Stream. Each step of the filter is registered. Unfortunately can't be automatically synthesized to 5x5 version, so parameter KERNEL_SIZE should be always 3.

sv_axis_median_5x5

Median filter 5x5 with AXI Stream interface. Each stage of processing is registered. Unfortunately can't be automatically synthesized to 3x3 version, so parameter KERNEL_SIZE should be always 5.

sv_cog

Module with AXI-Stream interface. Estimating center of energy of laser beam on image using center of gravity algorithm.

sv_gradient

sv_hist_eq

Histogram equalization module. Communication: AXIS. Settings: AXI-Lite

sv_qudrature_decoder

Quadrature decoder. Has AXI-Lite module for tuning from processor side. Main module is SystemVerilog, AXI-Lite is VHDL.

sv_remapper_12k

Custom algorithm of pixel remapping for Python12k (4 channels mode). Remapping algorithm from Datashit doesn't work, so we investigated and developed ours.

sv_trigger_gen

SV module. Use this module to generate trigger signal for python1300_ip_core. You could choose if trigger is external or an output of quad decoder module. Notice that we don't have any debouncing circuits here, only sync(two regs in a row for external trigger)

timestamp_adder

Module for adding timestamps to AXI Stream Image flow. Timestamp is 32bit, so this module puts value of timestamp to the first 4 bytes of image (4 pixels by 8 bit)

timestamp_timer

Simple time counter

uart

Simple UART core, just for training

ya_fifo

Simple synchronous one-clock FIFO. Test for academic purpose