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actstate

cadence-design-system-projects

cs_amplifer_current_mirror

CS Amplifier with active load and Current Mirror Biasing

ext_eeprom_i2c

hdlbit

heater-with-a-thermostat

hello-world

exploring git

mouse-modelling

multiplier-accumulator-control-using-voltage-control-oscillator

This work aims to design and implement two blocks: VCO block using eSIM and Multiplier-Accumulator (MAC) unit using Makerchip (converts Verilog code to Ngveri model file). Combining these two blocks will perform a Mixed Signal application as Multiplier-Accumulator control using voltage control oscillator (VCO).

omronmultimodetimer

potentiometric-dac-

sidastro30

Config files for my GitHub profile.

simple-uart-protocol-hdl-

start-up-circuit-with-zero-steady-state-current

A start-up circuit provide significant role in voltage & current ref. circuit which brings out the ref. circuit from zero current operating point to normal operating point and then is no longer used once the reference circuit starts operating properly. A conventional start-up circuit continues to consume constant current(mA) even after giving start-up. Thus increases the overall power consumption of circuit. This power can be multiple in numbers to bias generator circuits are deployed in a single chip, consequently reducing battery life. The start-up circuit discussed here overcome the above drawback as they turn off completely once the ref. circuit starts operating properly. By this circuit low power in IC design and small start-up time can be achieved.

task-scheduling-heterogeneous-system

Task Scheduling on Heterogeneous system

traffic-light-control-systems

verilogprojects

waffle-maker_fsm_c

Modelling the behaviour of the system using Extended Finite State Machine (EFSM)